Circuits and Techniques for 5G Mobile Communications and Low Power Sensors
The project consists of five parts that are separate, but are related in that they will develop critical circuits for 5G mobile communications and low power sensors.
Part 1 will explore several IC technologies for implementation of RF transmitter front-end chips for 5G systems with multiple antennas, and explore the linearity requirements and associated linearization techniques. To increase efficiency in backoff, architectures including Doherty and envelope tracking will be investigated. The impact on output fidelity of the mutual coupling between antennas will be examined. A major focus of the research will be on techniques that combine analog with digital predistortion techniques.
Part 2 will develop an interference cancelation technique applied to digital PLLs for frequency synthesis in 5G transceivers with carrier aggregation. In both 4G and anticipated 5G mobile communication systems, effective communication channel bandwidth is increased via carrier aggregation, i.e., combining multiple lower-bandwidth channels at different spectral locations. This requires multiple frequency synthesis PLLs to operate simultaneously at different frequencies on the same IC. A major practical problem is that each PLL output signal parasitically couples both modulated and unmodulated spurious tones into the other PLLs, often limiting overall performance. The research will develop an LMS-like algorithm to digitally measure the resulting interference components via correlation within the PLL and cancel them by introducing the opposite signals into the digitally controlled oscillator input, all in the digital domain.
Part 3 will develop computationally adaptive sampling and transmission techniques to extend the performance and efficiency of IoT/5G transceivers. The system to be developed consists of a low-noise amplifier with a switched bias scheme to have zero quiescent power, a low-power 10-bit SAR ADC using a novel charge recycling comparator (< 5 fJ/conv-step), a frequency tunable oscillator, an adaptive rate controller that determines the sampling frequency based on the signal activity, and an FSK transmitter. The novelty of this approach lies in quantifying the signal activity in a power efficient manner by computing the first and second order derivative of the signal. The objective is to reduce the power of the system to less than 50µW compared to 1mW using uniform sampling.
Part 4 will develop another technique for reducing power consumption in IoT recievers. It will reduce power consumption by avoiding PLL-based solutions in favor of a new architecture based on a single crystal, which can be readily found on any existing system, and a novel combination of injection-locked oscillators and variable frequency dividers. The target specifications are 16-QAM demodulation, 4Mbps data rate in 1MHz of bandwidth (compatible with Bluetooth channelization), -83 dBm sensitivity, all in <1mW of power consumption.
Part 5 will concentrate on the next generation of millimeter-wave phased arrays (60 GHz) and low-power radar sensors (80 GHz or 120 GHz) with emphasis on phased-array architectures for low DC power consumption while still maintaining excellent system-level capabilities. It will investigate different architectures for low-loss T/R switches including asymmetrical switches and bi-directional amplifiers, and do a full comparison between passive and active (vector modulator) phase shifters in terms of power consumption, linearity and bandwidth. It will also investigate power amplifier topologies with 10 dB output power control while still maintaining the same PAE, by using different size transistors connected in parallel. On the LO side, it will investigate the power consumption of a local oscillator and divider at 60 GHz for communications (80 GHz or 120 GHz for low-power radars) versus the use of an oscillator at 2x or 3x lower frequencies and a multiplier/amplifier chain. It will also study the transitions between the phased-array (or mm-wave radar) and the antennas, and how decrease the transition loss and also increase the antenna efficiency. The goal is to tackle every aspect of the circuit and antenna systems so as to reduce the power consumption while still maintaining a strong communication the link or detection range in range, and to demonstrate an efficient communications link and/or low power radar sensor.
Lead PI: Professor Ian Galton
Massive MIMO Systems
Massive MIMO (M-MIMO), which consists of a large number of antennas at the access point, is a promising technology to meet the high data rate and quality of service requirements of 5G wireless systems. In this project, CWC faculty addresses several challenges in M- MIMO system design. The topics include channel modeling and estimation, energy efficient techniques and hardware architectures. In particular, this project studies several key aspects of massive MIMO systems: channel estimation in different environments for frequency division duplex (FDD) systems, data-aided channel estimation for time division duplex (TDD) systems, and distributed massive MIMO design tradeoffs. In particular, the project considers a novel dictionary learning perspective to enable low dimensional representations of the channel and compressive channel learning that can significantly reduce the feedback overhead for FDD systems. Also part of the research plan includes the development of semi-blind channel estimation methods to improve channel estimation well beyond what is possible with pilot-only training as well as to address the pilot contamination problem. Low complexity receiver design that leverage the M-MIMO spatial degrees of freedom and physical layer techniques with low complexity hardware, i.e. reduced RF chains are also addressed in this research. Also of interest is energy efficiency at all levels; system, hardware and processing. Examining the main components that contribute to the base station (BS) power consumption, the project aims to adapt the number of active RF chains, a significant factor in the power budget, to reduce the total BS power consumption while satisfying the QoS requirements. A MIMO testbed is being planned to better understand the channel modeling and scalability issues.
Lead PI: Professor Bhaskar Rao
Hybrid Networking Techniques for Low-Latency Media-Rich Applications
With the ever increasing growth of media-rich applications from traditional video to virtual meeting/classrooms to tactile internet, the future networking paradigm will go away form a networking concept based on single-technology, single-flow, single-route model of information transfer, pushing the issues of usage prediction, integrated resource utilization and parallelism to all layers of protocol stack. Recent successful approaches, such as multi-homing, overlay networking, and distributed storage, deviate from this paradigm by using intelligent control to take advantage of redundancy and path diversity that already exist in the modern networks to provide a better experience to end-users.
Rather than treating the heterogeneous nature of the network and diversity of access technologies as an afterthought, this proposal considers an integrated approach that systematically takes advantage of various hybrid networking techniques to improve upon the network experience in general, and in particular upon latency in media-rich applications. These techniques include content caching, multicasting, multi-homing, multi-user coding, as well as braiding satellite+wifi+cellular technologies.
Lead PI's: Professor Sujit Dey and Professor Tara Javidi