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The proposed research consists of three parts: 1) Wideband VCO Modulation in
Fractional-N PLLs, 2) Combined DAC Noise Shaping and Cancellation for
High-Bandwidth DS ADCs, and 3) Direct Conversion Receiver
and VCO Improvements for 3G Mobile Systems. The three parts are closely related in
that they each address critical mixed-signal circuit implementation problems in modern wireless
communication systems.
Wireless communication systems invariably process analog signals because they
interface to the physical world which is inherently analog. For example, a
cellular telephone transmits and receives signals through its antenna in the form
of analog waveforms regardless of whether it is an "analog" or "digital" telephone.
However, in many situations digital circuits, wherein information is represented as
binary digits (bits) instead of current or voltage waveforms, offer numerous
advantages over analog circuits such as reduced cost, greater programmability,
virtually no variability over temperature changes and time, and amenability to
security encryption and automatic error correction. Therefore, the bulk of the
signal processing and control operations in most modern wireless communication
systems is done by digital circuitry. Often, the only significant analog circuitry
is that associated with the generation and reception of radio-frequency (RF) signals,
and the conversion of analog signals to and from digital form. Nevertheless, while
these analog functions represent only a small portion of the total signal processing
performed by a given communication system, they often represent much of the overall
cost of the system. The primary reason for this is that conventional techniques for
implementing the analog functions tend to be incompatible with the limitations
imposed by the integrated circuit technology used for digital circuitry, so they
are usually implemented with more expensive, but "analog-friendly" integrated
circuit technologies and off-chip components.
The proposed research involves the invention, development, analysis, and integrated
circuit implementation of critical mixed-signal (combined analog and digital)
wireless communication system blocks. The emphasis of the research is on the
development of digital signal processing techniques to mitigate the effects of
non-ideal analog circuit behavior in mixed-signal integrated circuits. The
resulting circuits will tend to blur the traditionally sharp analog-digital
dividing lines in communication systems in order to reduce the precision requirements
of the analog circuitry and thereby reduce the overall system cost.
The proposed research consists of three parts as outlined below. The three parts
will be conducted by different combinations of principal investigators, but are
closely related in that they each address critical mixed-signal circuit implementation
problems in modern wireless communication systems.
Part 1 of the proposed research will develop an enhancement to the conventional
delta-sigma (DS) fractional-N PLL architecture that
largely circumvents the tradeoff between phase noise and bandwidth yet is not
sensitive to component mismatches. The enhancement allows the PLL bandwidth to
be widened without incurring the usual phase noise penalty resulting from
insufficient filtering of the DS quantization noise.
Unlike other solutions to this problem, the proposed technique is not sensitive to
component mismatches, and does not require an extended-range phase detector or other
non-standard PLL components. As a proof-of-concept, a Bluetooth wireless LAN
compliant CMOS transmitter will be implemented based on the technique.
Part 2 of the proposed research will modify a DAC noise cancellation technique
originally developed by one of the PIs for pipelined ADCs to use with
mismatch-shaping DACs in DS ADCs. By combining DAC noise cancellation and
mismatch-shaping DACs, it is anticipated that DAC component mismatches can be
removed as the limiting factor in high dynamic range DS
ADCs with oversampling ratios below 10. As a proof of concept, a CMOS delta-sigma
ADC with an oversampling ratio of 8, and a target dynamic range of 90dB over a signal
bandwidth of 4MHz will be developed.
Part 3 of the proposed research consists of two tasks. The first task is to develop
an improved VCO, suitable for wide dynamic range applications. This circuit will
utilize innovative techniques to minimize the noise contributions from the active
components and maximize the signal swing at the output of the circuit, resulting in
a significant improvement in phase noise performance. The second task is to develop
a fully balanced sub-harmonic downconversion mixer topology with a substantial
improvement in second-order distortion. This will mitigate the well-known problems
of time varying dc offsets in direct conversion receivers. A background calibration
scheme will be developed that senses second order distortion components and modifies
the mixer bias to adaptively null them out, even with large and rapid variations in
the received signal strength. A proof-of-concept demonstration incorporating both
circuit approaches will be developed in an advanced BiCMOS technology.
The following CWC faculty are participating in this research project: Ian Galton(lead PI),
Larry Larson.
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Affiliated Faculty
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