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The objective of this project is to develop an on-chip network architecture
for interconnecting components on a System-on-Chip design. We expect to deliver
an on-chip network architecture that can be shown to be (1) scalable, (2) area
efficient, and (3) capable of supporting real-time traffic.
Broadband wireless communications applications demand enormous processing
power. Specialized semiconductor chips are used to provide the processing power
necessary for these applications. Such chips are usually composed of a large
number of internal modules. These modules may be processor blocks, memory
blocks, communication blocks, or custom logic blocks. Traditionally, these
modules are interconnected on the chip using ad-hoc global wiring. However, as
semiconductor chips become increasingly complex, designing with an ad-hoc global
wiring approach becomes increasingly difficult. In this project, we propose to
replace the ad-hoc global wiring with a structured on-chip packet network for
interconnecting the top-level modules of a semiconductor chip. We refer to this
approach as a Network-on-Silicon approach. We believe this new interconnection
paradigm will have a dramatic impact on the way future semiconductor chips will
be designed.
The proposed research is a part of a larger effort at UCSD called the
Mesh-Based Radios project to develop next-generation System-on-Chip
architectures for broadband wireless radio applications. In particular, we
propose to develop an on-chip interconnection network architecture for
interconnecting processing modules (e.g. RISC processors, memories, digital
communications building blocks, custom logic) together in a System-on-Chip
design. Before the end of the decade, a single chip will be able to hold
thousands of such modules. Instead of interconnecting these modules together by
routing dedicated wires, we propose to interconnect them by using a packet
switching network that routes packets between them. This global
Network-on-Silicon approach has many advantages over a traditional ad-hoc global
wiring approach. First, a structured network approach facilitates reusability
and interoperability of modules by standardizing on a common network interface.
Second, a structured network approach also greatly simplifies the design process
by encouraging modular design and by abstracting away the complexity of
inter-module communications. Third, a structured network approach can
significantly mitigate potentially severe crosstalk problems expected in
emerging nanoscale technologies by ensuring that the global wires have
well-controlled and optimized electrical properties. Finally, with
well-controlled electrical parameters, very aggressive high-speed circuits can
be used to significantly increase signal propagation speeds and reduce power
dissipation. The focus of this project will be to develop a scalable and area
efficient Network-on-Silicon architecture that can support both guaranteed and
best-effort traffic.
The following CWC faculty are participating in this research project: Bill Lin(lead PI).
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Affiliated Faculty
CoRe Research Projects